Xxxadul cam2 cam - Invalid register operand when updating

by  |  05-May-2020 17:15

wherein the address of the wide operand in the memory is aligned to result in a plurality of low order bits of the address to not be required for retrieval of the wide operand, and those low order bits provide the indicia of the size of the wide operand.13. The size of the result for additional instructions may not be so constrained, and so utilize dedicated storage to which the result operand is placed on execution of the instruction.

In a processor including a functional unit coupled to a first data path having a first bit width, a second data path having a second bit width greater than the first bit width, a plurality of third data paths having a combined bit width less than the second bit width, a wide operand storage storing a wide operand, a register file including registers having the first bit width, the register file being connected to the third data paths, a method comprising: further comprising a step of rounding the result elements by one of a plurality of rounding operations including round-to-nearest, round-to-zero, round-to-negative infinity, and round-to-positive infinity. The dedicated storage may be implemented in a local memory tightly coupled to the logic circuits that comprise the functional unit.

Namely, in each cycle, dependency checks are made by comparing the logical-register numbers shown as operands in the instructions, and the logical-register nwnbers are respectively renamed to appropriate physical-register numbers so that the dependencies would be dissolved. In regard to superscalar processors, it is desired to enhance performance by streamlining register renaming and decoding / issuing a larger number of instructions per cycle.

In the present invention, source and result operands are provided which are substantially larger than the data path width of the processor.

There is also a need for a processor system capable of efficient handling of operands and results of greater overall size than the entire general register file. In addition, several classes of instructions will be provided which cannot be performed efficiently if the source operands or the at least one result operand are limited to the width and accessible number of general purpose registers.

In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers.a functional unit capable of performing operations in response to instructions, coupled by the second data path to the wide operand storage, and coupled by the third data paths to the register file; andwherein the processor executes an instruction containing instruction fields specifying (i) a control register in the register file storing a control operand, and (ii) a results register in the register file, the instruction causing the functional unit to perform an operation using the control operand and the wide operand, and place the results of that operation in the results instruction causes the functional unit to perform an operation between elements contained in the wide operand and elements contained in the operand register, the elements being of a size specified by a control operand to thereby produce a plurality of results elements from which a value is stored in the results register. If the memory operand remains current—that is, the conditions are met—the memory operand fetch can be combined with one or more register operands in the functional unit, producing a result.

wherein the extraction is further controlled by fields in the control register which specify a shift amount from zero to the element size minus one and specify one of a plurality of rounding operations.wherein the address information for the wide operand stored in the memory is stored in the register file, and the address information includes both an address of the wide operand in the memory and an indicia of a size of the wide operand. The size of the result may be constrained to that of a general register so that no dedicated or other special storage is required for the result.

The technique involves maintaining, in a register list memory circuit having entries that respectively correspond to physical registers, a list of register assignments that assign logical registers to the physical registers. An instruction dependency exists between instructions (1) and (2) because instruction (1) reads data from register RI, and instruction (2) subsequently writes new data to register R1.

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